1. Field of the Invention
The present invention relates to a dynamic shift register circuit, and more specifically, to a dynamic shift register circuit for minimizing overlapping between two adjacent output pulses.
2. Descriptions of the Related Art
Recently, Thin-Film Transistor Liquid Crystal Display (TFT-LCD) has been widely utilized in personal computer display, TV, cell phones, and digital camera. Process technique nowadays can arrange the pixel arrays and the driving circuits of the liquid crystal display on a substrate for the aim of minimizing the cost and the weights thereof. The pixel arrays comprise a plurality of scanning lines and a plurality of signal lines while the driving circuits comprise a plurality of shift register circuits, electrically connected with each other, to output a plurality of horizontal and vertical scanning clock signals for driving each of the scanning lines and the signal lines respectively. Thus, display images inputted to the liquid crystal display are transmitted in turn to the related pixel arrays. If an overlapping phenomenon is occurred between two adjacent clock signals of the horizontal scanning and/or the vertical scanning clock signals, some pixels fail to correctly receive the image data or receive the image data which does not belong to them during receiving the image data. Therefore, part of image data will be incorrectly displayed on pixels which are not corresponding to that the display shown is not stable and the display quality is affected.
FIG. 1A illustrates a circuit diagram of a prior dynamic shift register circuit in U.S. Pat. No. 6,834,095. A complete shift register circuit can be made by electrically connecting a plurality of circuits shown in FIG. 1A in series. In FIG. 1A, CK represents a clock input signal, XCK represents an inverse clock input signal, (N−1)out represents an output end of a previous-stage shift register unit, (N)out represents an output end of the present stage shift register unit, (N+1)out represents an output end of a next-stage shift register. These output signals are used to drive the scanning lines and the signal lines of the pixel arrays. Please refer to FIG. 1B and FIG. 1C. FIG. 1B illustrates a voltage-to-time oscillograph of each stage of a prior dynamic shift register circuit shown in FIG. 1A and FIG. 1C illustrates an enlarged overlap-pulse oscillograph of the two stages while the simulation conditions of the above-mentioned waveform is: 50% duty cycle of the clock signal and the inverse clock signal, 2 volts of the threshold voltage of the transistor, and 10 pF of the load of the output end. From FIG. 1B, the overlapping phenomenon of these two signals of adjacent output ends is obvious. From FIG. 1C, the voltage of the cross point of the two overlapping output signals is about 10.7 volts.
To sum up, the signals of two adjacent output ends in the prior dynamic shift register circuit have a serious problem about an overlapping phenomenon. The voltage of the cross point thereof is also essentially high. Consequently, the possibility that the pixel arrays receive wrong image data is quite high. Moreover, the failure of sampling data will lead to serious distortion of display images. Only those problems are effectively solved the display quality of liquid crystal display or the like can be enhanced.